Integrated circuit package comprising surface capacitor and ground plane

An integrated circuit package comprising:

• a substrate comprising a first plurality of substrate pads;
• an integrated circuit die coupled to the first plurality of substrate pads embedded in a first layer of the substrate;
• a vertical capacitor having a first electrode, a second electrode and a first resistive layer, the first electrode coupled to the first resistive layer, the first resistive layer coupled to a first substrate pad embedded in the first layer of the substrate;
• and
• a conductive layer formed over a first surface and the second electrode of the vertical capacitor, wherein the conductive layer encapsulates the vertical capacitor, and wherein the first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.

An integrated circuit package comprising:

• a coreless substrate having a plurality of build-up layers;
• an integrated circuit die coupled to a first plurality of substrate pads embedded in a first layer of the plurality of build-up layers of the substrate;
• a vertical capacitor having first and second electrodes with a common axis being perpendicular to a planar surface of the substrate, the vertical capacitor further having a first insulating layer and a second insulating layer, the first insulating layer and the second insulating layer are formed over part of the first electrode, the first electrode is coupled to a first substrate pad embedded in the first layer of the substrate;
• and
• a conductive layer formed over the first insulating layer, the second insulating layer and the second electrode of the vertical capacitor, wherein the conductive layer encapsulates the vertical capacitor, wherein the plurality of build-up layers comprise two prepreg layers, and wherein each prepreg layer has a thickness range of 30-60 microns.