Method and device for incorporating single diffusion break into nanochannel structures of fet devices

A method of manufacturing a semiconductor device, comprising:

• providing a substrate having a working surface;
• forming a plurality of gate regions on the substrate, each gate region comprising a nanochannel structure;
• forming a plurality of source/drain (S/D) regions alternatingly arranged with the plurality of gate regions along the working surface such that sides of each S/D region are in contact with sides of the gate regions;
• forming an active gate in a first gate region of the plurality of gate regions, the active gate contacting the nanochannel structure of the first gate region to form an active nanochannel structure extending through the first gate region to a first side of an adjacent S/D region of the plurality of S/D regions;
• forming a dummy gate within a second gate region of the plurality of gate regions, the dummy gate contacting the nanochannel structure of the second gate region to form a dummy channel structure extending through at least a portion of the second gate region to a second side of the adjacent S/D region which is opposite to the first side of the adjacent S/D region;
• and
• forming an S/D structure in the adjacent S/D region such that the S/D structure extends from the active channel structure through the adjacent S/D region to the dummy nanochannel structure.

A method of manufacturing a semiconductor device, comprising:

• providing a substrate having a continuous multilayer FIN structure formed on the substrate and extending along a working surface of the substrate, wherein continuous multilayer FIN structure comprising a continuous nanochannel structure extending along the multilayer FIN structure;
• forming at least one single diffusion break cut in the continuous multilayer FIN structure to provide a plurality of active FIN structures separated by a respective single diffusion break cut, each active FIN structure comprising an active nanochannel structure;
• forming a plurality of gate cuts in each of the active FIN structures to provide a plurality of active gate regions from each active FIN structure, the plurality of active gate regions being separated by a respective one of the plurality of gate cuts and each active gate region comprising a respective active nanochannel extending through the active gate region;
• forming a single diffusion break structure in the single diffusion break cut, the single diffusion break structure comprising a dummy nanochannel structure surrounded by dielectric;
• forming source/drain S/D regions in each of the plurality of gate cuts, each S/D region comprising a S/D structure extending across the respective gate cut, wherein at least one S/D structure connects the dummy nanochannel to the active nanochannel of a respective active gate structure;
• and
• forming a plurality of active gate structures around the plurality of active nanochannels within respective active gate regions.