Read-assist circuits for memory bit cells employing a p-type field-effect transistor (pfet) read port(s), and related memory systems and methods

A method of reading data from a memory bit cell, comprising:

• pre-discharging at least one bitline coupled to an access node of one or more P-type Field-Effect Transistor (PFET) access transistors in a memory bit cell in response to a read operation;
• activating a wordline coupled to a gate of the one or more PFET access transistors in response to the read operation to transfer data from a storage circuit to the access node and the at least one bitline;
• and
• boosting a voltage in the memory bit cell, comprising positively boosting a voltage on the at least one bitline to positively boost a gate (G) voltage-to-source (S) voltage (Vgs) of the one or more PFET access transistors in response to the read operation to assist in transferring the data from the storage circuit to the access node.

A memory system, comprising:

• a memory array comprising one or more memory bit cell rows each comprising a plurality of memory bit cells, each memory bit cell of the plurality of memory bit cells in the one or more memory bit cell rows configured to provide data in response to a read operation;
• one or more wordlines each associated with a respective memory bit cell row among the one or more memory bit cell rows;
• each memory bit cell of the plurality of memory bit cells in each memory bit cell row among the one or more memory bit cell rows comprising one or more P-type Field-Effect Transistor (PFET) access transistors each comprising a gate configured to be activated by a wordline among the one or more wordlines associated with the memory bit cell row containing the memory bit cell in response to the read operation;
• one or more read-assist circuits each associated with one or more memory bit cells of the plurality of memory bit cells in the one or more memory bit cell rows, the one or more read-assist circuits configured to boost a voltage in the one or more memory bit cells in response to the read operation;
• and
• a plurality of bitline drivers each configured to activate a plurality of bitlines each associated with a respective memory bit cell column among one or more memory bit cell columns;
• wherein the one or more read-assist circuits comprise a plurality of bitline positive boost circuits coupled to the plurality of bitlines;
• and
• the plurality of bitline positive boost circuits is configured to positively boost a voltage on the plurality of bitlines in response to the read operation.