Timing error analysis method and information processing apparatus

An information processing apparatus comprising:

• a parameter extraction circuit configured to extract, from error information including a delay amount of a signal path in which a timing error has occurred and arrangement/wiring information of an element included in the signal path, a design value related to the delay amount of the signal path and a feature that is an input when a machine learning model learns with the design value as an output;
• a correct answer value estimation circuit configured to estimate a correct answer value of the design value from the feature and a machine learning model learning a relationship between the design value and the feature;
• a correct answer value comparison circuit configured to compare the design value with the correct answer value and storing a comparison result;
• a comparison result list generation circuit configured to generate a comparison result list including countermeasures for eliminating the timing error according to the comparison result;
• an error list generation circuit configured to aggregate signal paths included in the comparison result list for each design block and generate an error list including information indicating the signal paths aggregated for each of the design blocks and the countermeasures;
• and
• an error list output circuit configured to output the error list.

A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process for timing error analysis, the process comprising:

• extracting, from error information including a delay amount of a signal path in which a timing error has occurred and arrangement/wiring information of an element included in the signal path, a design value related to the delay amount of the signal path and a feature that is an input when a machine learning model learns with the design value as an output;
• estimating a correct answer value of the design value from the feature and a machine learning model learning a relationship between the design value and the feature;
• comparing the design value with the correct answer value and storing a comparison result;
• generating a comparison result list including countermeasures for eliminating the timing error according to the comparison result;
• aggregating signal paths included in the comparison result list for each design block to generate an error list including information indicating the signal paths aggregated for each of the design blocks and the countermeasures;
• and
• outputting the error list.