Optimizing dram memory based on read-to-write ratio of memory access latency
AssigneeHybris AG
InventorAhmad Hassan
Life of this patent
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AssigneeHybris AG
InventorAhmad Hassan
Estimating the term…
Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving a memory access latency value including a time to perform an operation with respect to the memory bank of the plurality of memory banks, receiving a set of operation percentages including an operation percentage for each of a plurality of operations performed on the memory bank, determining a probability associated with the memory access latency value using a mixture of Weibull distributions, described herein, comparing the probability to a threshold probability to provide a comparison, and selectively executing at least one action with respect to the memory bank based on the comparison.
A computer-implemented method for controlling operations performed on a memory bank of a plurality of memory banks, the method being executed by one or more processors, and comprising:
A non-transitory computer-readable storage medium coupled to one or more processors and having instructions stored thereon which, when executed by the one or more processors, cause the one or more processors to perform operations for controlling operations performed on a memory bank of a plurality of memory banks, operations comprising:
A system, comprising:
Dependencies are inferred from the claim text.