Ensuring a correct program sequence in a dual-processor architecture

A dual-processor module, comprising:

• a Processor A and a Processor B both coupled to a common memory;
• said Processor A and said Processor B each including a program counter for executing a logical sequence monitoring for dual-processors algorithm and a first safety program including a plurality of processor instructions in a program sequence to generate an instruction stream therefrom;
• said logical sequence monitoring algorithm implementing a method of ensuring a correct program sequence, comprising;
• at one or more selected points in time while said executing said first safety program, said Processor A reading a program counter value from its said program counter from a current instruction being executed and then calculating a current Processor A cyclic redundancy check (CRC) value from said program counter value corresponding to said instruction stream at said selected point in time in said program sequence, and said Processor B reading a program counter value from its program counter from said current instruction being executed and then calculating a current Processor B CRC value from said program counter value corresponding to said instructing stream at said selected point in time in said program sequence;
• at least one of said Processor A transferring its current CRC value to Processor B and said Processor B transferring its current CRC value to said processor A;
• comparing said current Processor A CRC value to said current Processor B CRC value, and
• triggering a safety action if said comparing determines that said current Processor A CRC value does not match said current Processor B CRC value.