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US 2019/0056450 A1Published application
Circuit structures to resolve random testability
AssigneeInternational Business Machines Corporation
InventorsRaghu G. GopalaKrishnaSetty, Mary P. Kusko, Spencer K. Millican
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Abstract
Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.
Claims6
A computer-implemented method for circuit structures for resolving random testability, the computer-implemented method comprising:
- analyzing logic structures of a circuit design;
- identifying the logic structures of the circuit design that are random resistant structures;
- replacing the identified logic structures with random testable structures;
- and
- performing a test of the circuit design including the random testable structures.
2 more elements
Dependencies are inferred from the claim text.