Method for integrating complementary metal-oxide-semiconductor (cmos) devices with microelectromechanical systems (mems) devices using a flat surface above a sacrificial layer

A method for manufacturing an integrated circuit (IC), the method comprising:

• forming a back-end-of-line (BEOL) interconnect structure and a sacrificial layer overlying a semiconductor substrate, wherein the BEOL interconnect structure comprises a dielectric layer, and further comprises multiple wires and multiple vias alternatingly stacked in the dielectric layer, and wherein the sacrificial layer is in the dielectric layer;
• performing a planarization into the dielectric layer and/or the sacrificial layer to form a planarized surface;
• forming a microelectromechanical systems (MEMS) structure overlying the sacrificial and dielectric layers, directly on the planarized surface;
• and
• removing the sacrificial layer after the forming of the MEMS structure to form a cavity in place of the sacrificial layer.

A method for manufacturing an integrated circuit (IC), the method comprising:

• forming an interconnect structure covering a substrate, wherein the interconnect structure comprises a dielectric layer, and further comprises multiple wires and multiple vias alternatingly stacked in the dielectric layer;
• forming a sacrificial layer sunken into the dielectric layer and having a top surface that is flush with a top surface of the dielectric layer;
• forming a microelectromechanical systems (MEMS) structure on the top surfaces of the sacrificial and dielectric layers;
• and
• removing the sacrificial layer after the forming of the MEMS structure to form a cavity in place of the sacrificial layer.