US 2018/0324379 A1Published application

Comparator for double ramp analog to digital converter

AssigneeOmniVision Technologies, Inc.

InventorsHiroaki Ebihara, Zheng Yang

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Abstract

A comparator includes a first stage coupled to compare a reference voltage to an image charge voltage signal. The first stage includes first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices to receive the reference voltage and the image charge voltage signal. A first auto-zero switch is between a gate of the first NMOS input transistor and a first node. The first node is between the first NMOS input transistor and the first cascode device. A second auto-zero switch is between a gate of the second NMOS input transistor and a second node. The second node is between the second cascode device and a second PMOS transistor. A voltage difference between the first and second nodes during an auto-zero period reduces an amount of kickback that occurs during an ADC period.

Claims13

Dependent claims

A comparator, comprising:

a first stage coupled to compare a reference voltage to an image charge voltage signal and provide a first output in response, the first stage including:
first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices, wherein gates of the first and second NMOS input transistors are coupled to receive the reference voltage and the image charge voltage signal, respectively;
a first auto-zero switch coupled between the gate of the first NMOS input transistor and a first node, the first node formed between the first NMOS input transistor and the first cascode device;
and
a second auto-zero switch coupled between the gate of the second NMOS input transistor and a second node, the second node formed between a second cascode device and a second PMOS transistor, wherein the second node is an output of the first stage,
wherein a voltage difference between the first and second nodes that the first and second NMOS input transistors are coupled to during an auto-zero period of operation of the comparator reduces an amount of kickback that occurs during an ADC period of operation of the comparator.

3 more elements

An imaging system, comprising:

an array of pixels to receive image light and generate an image charge voltage signal in response;
readout circuitry coupled to receive the image charge voltage signal from the array of pixels and provide a digital representation of the image charge voltage signal in response, the readout circuitry including a comparator to receive the image charge, compare the image charge voltage signal to a reference voltage, and provide the digital representation of the image charge voltage signal in response, wherein the comparator comprises:
a first stage coupled to receive the image charge and the reference voltage and provide a first output in response;
and
a second stage coupled to receive the first output and provide the digital representation of the image charge voltage signal in response, the second stage comprising:
an input coupled to receive the first output;
a first capacitor coupled to store a second stage reference voltage;
a reference voltage input coupled to the input, and further coupled to the first capacitor at a gate;
and
a first control switch coupled between the input and a third node of the first stage, and
wherein the first capacitor is charged to a voltage based on a voltage on the third node of the first stage in response to the first control switch being enabled.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/035,388Filed 13 Jul 2018
Priority: 27 Sep 2016
Published: 8 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 5/2481
Using field effect transistors: with at least one differential stage
H04N 25/671
Applied to fixed-pattern noise, e.g. non-uniformity of response: for non-uniformity detection or correction
H04N 25/78
Addressed sensors, e.g. MOS or CMOS sensors: readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H03K
Pulse technique

Family

Application15/277,648Division · filed 27 Sep 2016
Application16/035,388Division
US 10,079,990 B2Related patent
US 10,498,999 B2Related patent
US 2018/0091752 A1Published application
US 2018/0324379 A1This patent

From the US filing history. Foreign family members aren’t listed.

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