US 2018/0323956 A1 · DEVICE AND METHOD FOR RECOVERING CLOCK AND DATA

Abstract

A clock and data recovery device includes a data analysis circuit, a loop filter circuit, and a phase adjust circuit. The data analysis circuit is configured to generate an error signal according to input data, a first clock signal, and a second clock signal. The loop filter circuit is configured to generate an adjust signal according to the error signal. A phase filter circuit is configured to generate a first control signal according to the error signal. A switching element of a first frequency filter circuit is configured to output a second control signal according to the error signal and a first switching signal that has a first period. A first adder is configured to generate the adjust signal according to the first control signal and the second control signal. The phase adjust circuit is configured to adjust the first clock signal and the second clock signal.

Claims20

Dependent claims

A clock and data recovery device, comprising:

a data analysis circuit configured to generate an error signal according to input data, a first clock signal, and a second clock signal;
a loop filter circuit configured to generate an adjust signal according to the error signal, wherein the loop filter circuit comprises:
a phase filter circuit configured to generate a first control signal according to the error signal;
a first frequency filter circuit, wherein the first frequency filter circuit comprises a switching element, and the switching element is configured to output a second control signal according to the error signal and a first switching signal that has a first period;
and
a first adder configured to generate the adjust signal according to the first control signal and the second control signal;
and
a phase adjust circuit configured to adjust the first clock signal and the second clock signal according to the adjust signal.

5 more elements

A clock and data recovery method, comprising:

generating an error signal, by a data analysis circuit, according to an input data, a first clock signal, and a second clock signal;
generating a first control signal, by a phase filter circuit, according to the error signal;
outputting a second control signal with a first period, by a switching element of a first frequency filter circuit, according to the error signal and a first switching signal that has a first period;
generating an adjust signal, by a first adder, according to the first control signal and the second control signal;
and
adjusting the first clock signal and the second clock signal, by a phase adjust circuit, according to the adjust signal.

3 more elements

Dependencies are inferred from the claim text.

Device and method for recovering clock and data

Life of this patent

Device and method for recovering clock and data

Life of this patent

Abstract

Claims20