Characterization of in-chip error correction circuits and related semiconductor memory devices/memory systems

A method of validating an error correction code (ECC) circuit, comprising:

• 1) entering into a code validation mode;
• 2) generating a first error vector, the first error vector including at least one error bit;
• 3) writing the first error vector in a memory device;
• 4) reading a second error vector from the memory device, the second error vector being a result of performing an ECC operation on the first error vector by the ECC circuit included in the memory device;
• 5) checking positions of error bits included in the second error vector;
• 6) repeating step 2) to step 5) with different first error vectors until the error bits included in the second error vector are not correctable or until meeting a predetermined condition;
• 7) logging a pass/fail result, the pass/fail result based on whether the error bits included in the second error vector are not correctable at a rank level;
• and
• 8) exiting the code validation mode,
• wherein the method is performed by a memory controller.