US 2018/0323790 A1 · Counter-Based SYSREF Implementation

Abstract

A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.

Claims14

Dependent claims

A system, comprising:

an input flip-flop including a clock input terminal and a data input terminal configured to be coupled to a first reference signal, wherein the input flip-flop is configured to use first clock to latch the reference signal to produce a latched reference signal;
a counter coupled to the input flip-flop and configured to count pulses of the first clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the first clock;
and
a clock tree configured to divide down the first clock to generate a first output clock;
wherein the clock tree is configured to be synchronized by a pulse of the second reference signal.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/036,221Filed 16 Jul 2018

Priority

30 Dec 2016

Published

8 Nov 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03L 7/08
Using a reference signal applied to a frequency- or phase-locked loop: details of the phase-locked loop
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…

Counter-Based SYSREF Implementation

Life of this patent

Counter-Based SYSREF Implementation

Life of this patent

Abstract

Claims14