Dynamic decode circuit with delayed precharge
AssigneeInternational Business Machines Corporation
InventorsPaul Alan Bunce, Yuen Hung Chan, John D Davis, Antonio Raffaele Pelella
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Abstract
A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.
Claims17
A dynamic decode circuit connected between a first power source and a second power source, the dynamic decode circuit comprising a decoder connected to a first node and an evaluate clock circuit connected to a second node, wherein the decoder is configured to decode a plurality of inputs, wherein the evaluate clock circuit is configured to present a result of the decode to the second node, wherein the first node of the decoder is conductively connected to a base of a first transistor of the evaluate clock circuit, and
- wherein the dynamic decode circuit further comprises one or more precharge circuits, wherein at least one of the one or more precharge circuits is a delay precharge circuit, wherein the delay precharge circuit consists of a respective first precharge transistor serially connected to a respective second precharge transistor, wherein a base of the first precharge transistor is configured to receive an evaluation clock signal, and a base of the second precharge transistor is configured to receive a delayed evaluation clock signal, each precharge circuit is conductively connected to the second power source, wherein the each precharge circuit is configured to precharge a respective node based on the evaluation clock signal being inactive, and the precharge circuit configured to not conduct based on the evaluation clock signal being active,
- wherein the first node is conductively connected to a first delay precharge circuit.
A dynamic decode circuit connected between a first power source and a second power source, the dynamic decode circuit comprising a decoder connected to a first node and an evaluate clock circuit connected to a second node, wherein the decoder is configured to decode a plurality of inputs, wherein the evaluate clock circuit is configured to present a result of the decode to the second node, wherein the first node of the decoder is conductively connected to a base of a first transistor of the evaluate clock circuit, and
- wherein the dynamic decode circuit further comprises one or more precharge circuits, wherein at least one of the one or more precharge circuits is a delay precharge circuit,
- wherein each delay precharge circuit is configured to start a precharge of a respective node a predetermined delay after an evaluation clock signal going inactive, wherein the each delay precharge circuit is configured to end the precharge of the respective node the evaluation clock signal going active,
- wherein the first node is conductively connected to a first delay precharge circuit.
Dependencies are inferred from the claim text.