Metal oxide semiconductor varactor quality factor enhancement
AssigneeQUALCOMM Incorporated
InventorPhanikumar KONKAPAKA
Life of this patent
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Abstract
An integrated circuit formed with a process that enables multiple types of gate stacks improves a quality factor of metal oxide semiconductor (MOS) varactors at the device level. In one instance, the integrated circuit includes multiple first type transistors having a first gate stack with a first resistance and multiple second type transistors having a second gate stack with a second resistance that is higher than the first resistance. The integrated circuit also includes a metal oxide semiconductor varactor having the first gate stack with the first resistance.
Claims18
An integrated circuit formed with a process that enables multiple types of gate stacks, the integrated circuit comprising:
- a plurality of first type transistors having a first gate stack with a first resistance;
- a plurality of second type transistors having a second gate stack with a second resistance that is higher than the first resistance;
- and
- a metal oxide semiconductor varactor having the first gate stack with the first resistance.
A method of fabricating an integrated circuit (IC) with multiple types of gate stacks comprising:
- fabricating a plurality of first type transistors having a first gate stack with a first resistance;
- fabricating a plurality of second type transistors having a second gate stack with a second resistance that is higher than the first resistance;
- and
- fabricating a metal oxide semiconductor varactor having the first gate stack with the first resistance.
An integrated circuit formed with a process that enables multiple types of gate stacks, the integrated circuit comprising:
- a plurality of first type transistors having a first gate stack with a first resistance;
- a plurality of second type transistors having a second gate stack with a second resistance that is higher than the first resistance;
- and
- means for storing energy in an electrical field, the energy storing means comprising the first gate stack with the first resistance.
Dependencies are inferred from the claim text.