Charge Trapping Split Gate Device and Method of Fabricating Same

A split gate device, comprising:

• a select gate disposed over a substrate;
• a memory gate disposed over the substrate;
• a dielectric structure having a first portion disposed between the memory gate and the substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate;
• first and second silicide layers disposed over the select gate and the memory gate respectively;
• and
• a spacer formed over the select gate along an inner sidewall of the memory gate, the spacer covering a portion of the inner sidewall of the memory gate that extends above a top surface of the select gate.

A device, including:

• a substrate divided into a core region and a periphery region,
• wherein the core region comprises at least one memory device formed on the substrate, each memory device including,
• a select gate disposed adjacent to a memory gate over the substrate,
• a dielectric structure having a first portion disposed underneath the memory gate and a second portion disposed between and separating the select gate from the memory gate,
• a spacer formed over the select gate, insulating the memory gate and select gate from one another, and
• wherein the periphery region comprises at least one first type of transistor and at least one second type of transistor formed on the substrate, wherein a first gate dielectric of the at least one first type of transistor is thicker than a second gate dielectric of the at least one second type of transistor.

A system-on-chip (SOC) device, comprising:

• a memory array including a plurality of memory cells, wherein each memory cell includes,
• a select gate disposed adjacent to a memory gate and over a substrate, wherein a top surface of the memory gate has a greater elevation than a top surface of the select gate,
• a dielectric structure having a first portion disposed underneath the memory gate and a second portion disposed between and separating the select gate from the memory gate,
• a spacer formed over the select gate, insulating the memory gate and select gate from one another;
• and
• a peripheral circuitry comprising,
• a plurality of first transistors, each first transistor including a first gate dielectric disposed underneath a first gate, and
• a plurality of second transistors, each second transistor including a second gate dielectric disposed underneath a second gate,
• wherein the first gate dielectric has a greater thickness than the second gate dielectric, and wherein top surfaces of the first and second gates have an approximately same elevation.