Method of making a cmos semiconductor device using a stressed silicon-on-insulator (soi) wafer
AssigneeSTMicroelectronics S.r.l.
InventorsQing Liu, Nicolas Loubet
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AssigneeSTMicroelectronics S.r.l.
InventorsQing Liu, Nicolas Loubet
Estimating the term…
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.
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Dependencies are inferred from the claim text.