Vertical iii-n transistors with lateral epitaxial overgrowth

A III-N transistor, comprising:

• a drain comprising a III-N material with an impurity at a first concentration;
• a drift region over the drain, the drift region comprising a III-N material with an impurity at a second concentration, less than the first concentration;
• a channel over the drift region, the channel comprising a III-N material;
• a gate electrode over the channel;
• and
• a source coupled to the channel.

An integrated circuit (IC), comprising:

• a pair of III-N transistors over a silicon substrate, each transistor further comprising:
• a gate electrode over a channel region, the channel region comprising a Group III element and nitrogen;
• a source coupled to the channel region on either side of the gate electrode, the source comprising a Group III element, nitrogen, and a donor impurity having at least a first concentration;
• a drain coupled to the channel region and opposite the gate electrode, wherein the drain is coupled to channel region through a drift region comprising a Group III element, nitrogen, and a donor impurity having a second concentration, less than the first concentration;
• and
• a drain contact between a source of a first of the transistors and a source of a second of the transistors, wherein the drain contact is coupled to a drain of each of the transistors.

A method of forming a III-N transistor, the method comprising:

• epitaxially growing a first III-N material on a substrate, the first III-N material comprising a first concentration of donor impurities;
• epitaxially growing a second III-N material from a surface of the first III-N material to backfill a trench in an amorphous layer that is over a portion of the first III-N material, wherein the second III-N material has a second concentration of donor impurities, less than the first concentration;
• epitaxially growing a third III-N material from a surface of the second III-N material;
• forming a gate electrode over the third III-N material;
• forming drain contact metallization through the amorphous layer and contacting the first III-N material;
• and
• forming source contact metallization coupled to the third III-N material.

A method of fabricating an integrated circuit, the method comprising:

• forming a pair n+ doped III-N semiconductor drains over two adjacent substrate regions;
• epitaxially growing an n− doped III-N semiconductor drift region from each of the pair of drains, the growing confined to within a trench in an amorphous layer that is over a portion of the drains;
• epitaxially growing a pair of III-N semiconductor bodies from a surface of the n− doped III-N semiconductor with growth conditions that expand the III-N semiconductor islands laterally over a top surface of the amorphous layer;
• forming a pair of gate electrodes, over a channel portion of the III-N semiconductor bodies;
• and
• forming drain contact metallization through the amorphous layer and contacting both of the pair of III-N drains.