US 2018/0323296 A1Published application

Method for manufacturing a hemt transistor and hemt transistor with improved electron mobility

AssigneeSTMicroelectronics S.r.l.

InventorsFerdinando Iucolano, Andrea Severino, Maria Concetta Nicotra, Alfonso Patti

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Abstract

A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

Claims20

Dependent claims

A transistor, comprising:

a semiconductor body;
a first dielectric layer on the semiconductor body;
an opening extending through the first dielectric layer, the opening having sidewalls and a bottom surface;
an interface layer on the sidewalls of the opening;
a second dielectric layer formed on the interface layer;
a gate electrode positioned at least partially in the opening and on the second dielectric layer;
a source contact having a first portion and a second portion, the first portion of the source contact extending through the first dielectric layer and into the semiconductor body in a first direction, the second portion of the source contact extending on the second dielectric layer in a second direction that is transverse to the first direction;
and
a drain contact having a first portion and a second portion, the first portion of the drain contact extending through the first dielectric layer and into the semiconductor body in the first direction, the second portion of the drain contact extending on the second dielectric layer in the second direction.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/020,807Filed 27 Jun 2018
Priority: IT 10201500007211412 Nov 2015
Published: 8 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 30/4735
Using Group III-V semiconductor material: having delta-doped or planar-doped donor layers
H10D 30/015
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
H10D 30/4732
Having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT: using Group III-V semiconductor material
H10D 30/475
High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]: having wider bandgap layer formed on top of lower bandgap…

Family

Application15/156,740Division · filed 17 May 2016
Application15/832,680Continuation · filed 5 Dec 2017
Application16/020,807Continuation
Application15/832,680Division
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US 2018/0323296 A1This patent

From the US filing history. Foreign family members aren’t listed.

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