Power device with high aspect ratio trench contacts and submicron pitches between trenches

A semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area wherein the semiconductor power device further comprising:

• a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches covered by a high density plasma (HDP) insulation layer wherein the HDP insulation layer vertically sticks out above the gate trenches;
• spacers attached to a top portion of the HDP insulation layer above the gate trenches and exposing a top surface of mesa areas of the semiconductor substrate between the gate trenches;
• and
• each of the mesa areas between the gate trenches having a deep contact trench vertically aligned with the spacers and extending vertically below a top surface of the conductive materially partially filling the trench gate wherein the recessed contact trenches are filled with a source/body contact material.