Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a finfet device

A method of forming a FinFET device, comprising:

• forming a gate around an initial fin structure and above a layer of insulating material, wherein said initial fin structure positioned in a source/drain region of said device comprises an exposed portion of said initial fin structure that is positioned above a level of an upper surface of said layer of insulating material, said exposed portion of said initial fin structure in said source/drain region having a first height above said upper surface of said layer of insulating material and a first lateral width at a location that is approximately level with said upper surface of said layer of insulating material;
• performing a fin trimming process on said exposed portion of said initial fin structure in said source/drain region of said device so as to produce a reduced-size fin portion positioned above said upper surface of said layer of insulating material, said reduced-size fin portion having a second height above said upper surface of said layer of insulating material and a second lateral width at a location adjacent an upper surface of said reduced-size fin portion, wherein said second height is less than said first height and said second width is less than said first width;
• forming a conformal and rectangular-shaped epi semiconductor material on an upper surface and sidewall surfaces of said reduced-size fin portion
• positioned above said upper surface of said layer of insulating material, wherein said sidewall surfaces extend in a direction parallel to an axial length of said reduced-size fin portion;
• and
• forming a conductive source/drain contact structure that is conductively coupled to and is wrapped around said conformal and rectangular-shaped epi semiconductor material.

A method of forming a FinFET device, comprising:

• forming a gate comprising a gate structure and a sidewall spacer positioned adjacent said gate structure around an initial fin structure and above a layer of insulating material, wherein said initial fin structure positioned in a source/drain region of said device comprises an exposed portion of said initial fin structure that is positioned above a level of an upper surface of said layer of insulating material and not covered by said gate, said exposed portion of said initial fin structure having a first size;
• performing a fin trimming process on said exposed portion of said initial fin structure after forming said sidewall spacer so as to produce a reduced-size fin portion positioned above said upper surface of said layer of insulating material in said source/drain region of said device, said reduced-size fin portion having a second size that is less than said first size;
• forming a conformal epi semiconductor material on an upper surface and sidewall surfaces of said reduced-size fin portion, wherein said sidewall surfaces extend in a direction parallel to an axial length of said reduced-size fin portion;
• and
• forming a conductive source/drain contact structure that is conductively coupled to and wrapped around said conformal epi semiconductor material.