US 2018/0323255 A1 · ON-CHIP MIM CAPACITOR

Abstract

A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.

Claims20

Dependent claims

A device having an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices, comprising:

a first capacitor electrode formed between gate structure regions in a capacitor region and formed from contact metal for contacts to source and drain (S/D) regions in a CMOS region;
an insulator formed in contact with the first electrode in the gate structure regions in the capacitor region;
and
a second electrode formed in a plurality of loops in contact with the insulator within the gate structure regions in the capacitor region to form the on-chip capacitor.

1 more element

Dependencies are inferred from the claim text.

On-chip mim capacitor

Life of this patent

On-chip mim capacitor

Life of this patent

Abstract

Claims20