Image sensor

An image sensor including a plurality of pixels, each pixel comprising:

• a semiconductor substrate doped with a first dopant type;
• a first insulated vertical electrode that delimits a photosensitive area doped with a second dopant type, wherein the first insulated vertical electrode is electrically connected to receive a first bias voltage;
• a second insulated vertical electrode and a third insulated vertical electrode that delimit a charge storage area doped with said second dopant type, wherein the second and third insulated vertical electrodes are physically separate from each other but electrically connected to receive a second bias voltage;
• wherein said first insulated vertical electrode and said third vertical electrode extend parallel to each other with a first portion of said semiconductor substrate doped with the first dopant type positioned in contact with and extending between said first and third vertical electrodes;
• and
• wherein the third insulated vertical electrode extends between the charge storage area and the photosensitive area, and wherein the second insulated vertical electrode comprises a first portion extending parallel to a length of the third insulated vertical electrode and a second portion extending perpendicular to the first portion opposite a first end of the third insulated vertical electrode.

An image sensor including a plurality of pixels, each pixel comprising:

• a semiconductor substrate doped with a first dopant type;
• a first insulated vertical electrode that delimits a photosensitive area doped with a second dopant type, wherein the first insulated vertical electrode is electrically connected to receive a first bias voltage;
• a second insulated vertical electrode and a third insulated vertical electrode that delimit a charge storage area doped with said second dopant type, wherein the second and third insulated vertical electrodes are physically separate from each other but electrically connected to receive a second bias voltage;
• wherein said first insulated vertical electrode and said third vertical electrode extend parallel to each other with a first portion of said semiconductor substrate doped with the first dopant type positioned in contact with and extending between said second and fourth vertical electrodes;
• and
• a fourth insulated vertical electrode positioned between the second and third insulated vertical electrodes that divides the charge storage area into a first charge storage area and a second charge storage area, wherein the second, third, and fourth insulated vertical electrodes are physically separate from each other but electrically connected to receive said second bias voltage.