Three-dimensional semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorsCHANGHYUN LEE, CHANJIN PARK, BYOUNGKEUN SON, SUNG-IL CHANG
Life of this patent
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Abstract
A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
Claims15
-42. (canceled)
A three-dimensional semiconductor device comprising:
- a semiconductor substrate, an underlying layer on the semiconductor substrate, and a first structure on the underlying layer;
- an opening penetrating at least the first structure;
- an insulating layer on an inner wall of the opening;
- a recessed hole disposed at a lower end of the opening and exposing a portion of the semiconductor substrate;
- an insulating spacer in the opening;
- and
- a semiconductor pattern covering the insulating spacer in the opening and being in direct contact with an inner wall of the recessed hole,
- wherein a bottom surface of the insulating spacer is positioned at a vertical level equivalent to or higher than an uppermost surface of the semiconductor substrate.
A three-dimensional semiconductor device, comprising:
- a semiconductor substrate;
- an underlying layer on the substrate;
- a first structure on the underlying layer, the first structure including three-dimensionally arranged memory devices and having a first semiconductor pattern penetrating the first structure;
- and
- a second structure on the first structure, the second structure including at least a conductive pattern and having a second semiconductor pattern penetrating the second structure,
- wherein the first structure and the second structure electrically is connected to each other via the first semiconductor pattern and the second semiconductor pattern, and a lower end of the second semiconductor pattern is disposed on and proximal to an upper end of the first semiconductor pattern, and a lower end of the first semiconductor pattern is in contact with the semiconductor substrate and an upper end of the second semiconductor pattern is electrically connected to a bit line.
Dependencies are inferred from the claim text.