Vertical division of three-dimensional memory device

A method comprising:

• forming a stack of alternating layers of a first material and a second material over a substrate;
• forming an opening in the stack of alternating layers;
• forming a multi-layer dielectric on an inside wall of the opening, and a charge-trapping layer overlying the blocking layer;
• forming a channel layer overlying the multi-layer dielectric;
• forming a first vertical trench substantially perpendicular to the substrate and dividing the multilayer dielectric and channel layer to form a plurality of vertical memory cell strings, the plurality of vertical memory cell strings including first and second memory cell strings;
• forming at least one channel connection pillar in the first vertical trench electrically and physically reconnecting channel layers of the first and second memory cell strings;
• and
• forming a first isolation dielectric layer in the first vertical trench.

A method, comprising:

• forming a plurality of vertical memory cell strings within an opening disposed in a stack of alternating layers of a first layer and a second layer over a substrate, wherein forming the plurality of vertical memory cell strings comprises:
• forming a multi-layer dielectric including a blocking layer overlying an inside wall of the opening, and a charge-trapping layer overlying the blocking layer;
• forming a channel layer overlying the multi-layer dielectric;
• forming a first vertical trench substantially perpendicular to the substrate and dividing the multilayer dielectric and channel layer to form the plurality of vertical memory cell strings, wherein the plurality of vertical memory cell strings include first and second memory cell strings;
• reconnecting channel layers of the first and second memory cell strings;
• and
• forming a first isolation dielectric layer in the first vertical trench,
• wherein reconnecting the channel layer comprises forming at least one channel connection pillar in the first vertical trench electrically and physically connects the channel layers of the first and second memory cell strings.

A method, comprising:

• forming a three-dimensional (3D) memory array including a plurality of vertical NAND strings, each formed within an opening disposed in a stack of alternating layers of a dielectric layer and a sacrificial gate layer over a substrate, wherein forming the plurality of vertical NAND strings comprises:
• forming a multilayer dielectric overlying an inside wall of the opening;
• forming a channel layer overlying the multi-layer dielectric;
• removing the sacrificial gate layer using a wet etch process;
• depositing a conductive material in contact with the multilayer dielectric, to form a gate layer;
• forming a vertical trench substantially perpendicular to the substrate and vertically dividing the stack of alternating layers, the multilayer dielectric and the channel layer to form from each of the plurality of vertical NAND strings two half vertical NAND strings separated by the vertical trench;
• reconnecting channel layers of the plurality of vertical NAND strings;
• and
• forming an isolation dielectric pillar in the vertical trench,
• wherein reconnecting the channel layers comprises forming channel connection pillars in the vertical trench to electrically and physically connects the channel layers of the plurality of vertical NAND strings.