Back to results
US 2018/0323196 A1Published application
Method and circuit for integrated circuit body biasing
AssigneesSTMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
InventorsFlorian Cacho, Vincent Huard
Life of this patent
Estimating the term…
Abstract
The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.
Claims20
An integrated circuit comprising:
- a plurality of circuit domains, each circuit domain including:
- p-type and n-type wells;
- a plurality of transistor devices positioned over the p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain;
- a monitoring circuit that, in operation, detects when a slack time of at least one of the data paths in the circuit domain falls below a threshold level, and generates an output signal on an output line based on said detection;
- and
- a biasing circuit that, in operation, modifies a biasing voltage of at least one of the n-type or p-type well of the circuit domain, wherein the p-type and n-type wells in each circuit domain comprise a plurality of p-type wells electrically coupled together and a plurality of n-type wells electrically coupled together and said n-type and p-type wells extend across the plurality of circuit domains.
3 more elements
A method comprising:
- in each circuit domain of a plurality of circuit domains of an integrated circuit that include a plurality of monitoring circuits, respective, and a plurality of biasing circuits, respectively, detecting, by the monitoring circuit in the circuit domain, when a slack time of at least one data path in the circuit domain falls below a threshold level and generating an output signal on an output line based on said detecting, wherein each circuit domain comprises a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain;
- and
- in each circuit domain, modifying, by the biasing circuit of the circuit domain, a biasing voltage of at least one of the n-type wells and p-type wells of the circuit domain, wherein the p-type and n-type wells in each circuit domain comprise a plurality of p-type wells electrically coupled together and a plurality of n-type wells electrically coupled together and said n-type and p-type wells extend across the plurality of circuit domains.
An integrated circuit comprising:
- a plurality of circuit domains, each circuit domain including:
- p-type and n-type wells;
- one or more data paths positioned over the p-type and n-type wells;
- a monitoring circuit that, in operation, detects when a slack time of at least one of the data paths in the circuit domain falls below a threshold level, and generates an output signal on an output line based on said detection;
- and
- a biasing circuit that, in operation, modifies a biasing voltage of at least one of the n-type and p-type wells of the circuit domain based on said output signal, wherein each circuit domain comprises at least one of:
- a p-type well enclosing an n-type well, and
- an n-type well enclosing a p-type well.
5 more elements
An integrated circuit comprising:
- a plurality of circuit domains, each circuit domain including:
- p-type and n-type wells;
- one or more data paths positioned over the p-type and n-type wells;
- a monitoring circuit that, in operation, detects when a slack time of at least one of the data paths in the circuit domain falls below a threshold level, and generates an output signal on an output line based on said detection;
- and
- a biasing circuit that, in operation, modifies a biasing voltage of at least one of the n-type and p-type wells of the circuit domain based on said output signal;
- and
- an insulating strip positioned between one or more n-type wells of a first of said circuit domains and one or more n-type wells of a second of said circuit domains, and between one or more p-type wells of the first of said circuit domains and one or more p-type wells of the second of said circuit domains.
5 more elements
Dependencies are inferred from the claim text.