Stacked channel structures for mosfets

A circuit element, comprising:

• a semiconductor substrate;
• a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region;
• a first strained channel of a first transistor, wherein the first strained channel is disposed in the lower region;
• a second strained channel of a second transistor, wherein the second strained channel is disposed in the upper region, and the first strained channel is disposed between the second strained channel and the semiconductor substrate;
• and
• a conductive pathway disposed between the first and second transistors.

A method of manufacturing a stacked channel structure, comprising:

• providing a semiconductor substrate having a substrate lattice constant;
• providing a first intermediate layer on the semiconductor substrate;
• providing a first channel material on the first intermediate layer, the first channel material having a first lattice constant different from the substrate lattice constant;
• providing a second intermediate layer on the first channel material;
• providing a second channel material on the second intermediate layer, the second channel material having a second lattice constant different from the substrate lattice constant;
• and
• forming a fin extending away from the semiconductor substrate, wherein the first channel material is disposed in a lower region of the fin and the second channel material is disposed in an upper region of the fin.

A computing device, comprising:

• a memory device;
• and
• a processing device, coupled to the memory device, wherein the processing device includes a circuit element that includes:
• a semiconductor substrate,
• a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region,
• a first strained channel of a first transistor, wherein the first strained channel is disposed in the lower region,
• a second strained channel of a second transistor, wherein the second strained channel is disposed in the upper region, and the first strained channel is disposed between the second strained channel and the semiconductor substrate, and
• a conductive pathway disposed between the first and second transistors.