Fin-type field effect transistors with single-diffusion breaks and method

A semiconductor structure comprising:

• a semiconductor fin having a first top surface and first opposing sides;
• isolation regions in the semiconductor fin and having second top surfaces that are substantially co-planar with the first top surface of the semiconductor fin and further having second opposing sides;
• isolation bumps on the isolation regions, respectively, and having third top surfaces;
• bump sidewall spacers positioned laterally adjacent to the isolation bumps and having at least outer portions above and immediately adjacent to the first top surface of the semiconductor fin;
• non-functional gate structures being above and immediately adjacent to the third top surfaces of the isolation bumps;
• a transistor between the isolation regions and comprising:
• source/drain regions in the semiconductor fin;
• a channel region within the semiconductor fin and positioned laterally between the source/drain regions such that each source/drain region has a first side adjacent to the channel region and a second side opposite the first side so as to be adjacent to but physically separated from one of the isolation regions;
• and
• a functional gate structure adjacent to the first top surface and the first opposing sides of the semiconductor fin at the channel region;
• gate sidewall spacers positioned laterally adjacent to the non-functional gate structures and the functional gate structure, wherein any of the gate sidewall spacers that are positioned laterally adjacent to the non-functional gate structures are above and immediately adjacent to the third top surfaces of the isolation bumps and further extend laterally onto the bump sidewall spacers;
• and
• a dielectric layer adjacent to the first opposing sides of the semiconductor fin at the source/drain regions and the second opposing sides of the isolation regions, wherein the isolation bumps extends laterally beyond the second opposing sides of the isolation regions onto the dielectric layer.

A semiconductor structure comprising:

• a semiconductor fin having a first top surface and first opposing sides;
• isolation regions in the semiconductor fin and having second top surfaces that are substantially co-planar with the first top surface of the semiconductor fin and further having second opposing sides;
• isolation bumps on the isolation regions, respectively, and having third top surfaces;
• bump sidewall spacers positioned laterally adjacent to the isolation bumps and having at least outer portions above and immediately adjacent to the first top surface of the semiconductor fin, wherein the bump sidewall spacers have fourth top surfaces that are at or below a level of the third top surfaces;
• non-functional gate structures being above and immediately adjacent to the third top surfaces of the isolation bumps;
• a transistor comprising:
• source/drain regions in the semiconductor fin;
• a channel region within the semiconductor fin and positioned laterally between the source/drain regions such that each source/drain region has a first side and a second side opposite the first side, the first side being adjacent to the channel region and the second side being adjacent to but physically separated from one of the isolation regions and further below one of the bump sidewall spacers;
• and
• a functional gate structure adjacent to the first top surface and the first opposing sides of the semiconductor fin at the channel region, wherein the functional gate structure and the non-functional gate structure comprise replacement metal gate structures;
• gate sidewall spacers positioned laterally adjacent to the non-functional gate structures and the functional gate structure, wherein any of the gate sidewall spacers that are positioned laterally adjacent to the non-functional gate structures are above and immediately adjacent to the third top surfaces of the isolation bumps and further extend laterally onto the bump sidewall spacers;
• and
• a dielectric layer adjacent to the first opposing sides of the semiconductor fin at the source/drain regions and the second opposing sides of the isolation regions, wherein the isolation bumps extends laterally beyond the second opposing sides of the isolation regions and onto the dielectric layer and wherein the non-functional gate structures and the functional gate structure have substantially co-planar top surfaces such that a first height of the non-functional gate structures as measured from the third top surfaces of the isolation bumps is less than a second height of the functional gate structure as measured from the first top surface of the semiconductor fin.