High Voltage Electrostatic Discharge (ESD) Protection

An electrostatic discharge (ESD) protection circuit comprising:

• a first transistor of a first dopant type having a first emitter and a first base both electrically coupled to a first voltage terminal and a first connector electrically coupled to a second voltage terminal;
• a second transistor of a second dopant type having a second emitter and a second base both electrically coupled to the first collector and a second collector electrically coupled to the first base;
• and
• a third transistor of the first dopant type having a third emitter and a third base tied to the first emitter and the first base, respectively, and a third connector electrically coupled to the second voltage terminal, wherein the second emitter is arranged between the first connector and the third connector and adjacent to both the first connector and the third connector,
• wherein the first transistor is operable to be turned on by a trigger voltage applied between the first voltage terminal and the second voltage terminal to generate a first trigger current,
• wherein the third transistor is operable to be turned on by the trigger voltage to generate a second trigger current, and
• wherein the second transistor is operable to be turned on by the first trigger current and the second trigger current and conduct an electrostatic discharge current between the first voltage terminal and the second voltage terminal.

A method of fabricating an electrostatic discharge (ESD) protection device on a substrate, the method comprising:

• forming a base well of a first dopant type on the substrate;
• forming a first well of the first dopant type and a second well of a second dopant type in the base well;
• forming a first highly doped region of the first dopant type and a second highly doped region of the second dopant type in the first well;
• forming a third highly doped region of the second dopant type in the second well;
• forming a fourth highly doped region of the first dopant type in the third highly doped region;
• and
• forming electric contacts for electrically coupling the first highly doped region and the second highly doped region to a first voltage terminal and the third highly doped region and the fourth highly doped region to a second voltage terminal,
• wherein the first highly doped region, the second highly doped region, and the third highly doped region constitute a first transistor, and the first highly doped region, the third highly doped region, and the fourth highly doped region constitute a second transistor, the first transistor and the second transistor being operably parallel between the first voltage terminal and the second voltage terminal.