Surface finishes for high density interconnect architectures
AssigneeIntel Corporation
InventorsDavid Unruh, Srinivas V. Pietambaram
Life of this patent
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Abstract
An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.
Claims20
An apparatus including a package comprising
- a first pair of nickel, palladium, tin (NPT) stacks formed in a solder resist of the package, the first pair of NPT stacks having a first pitch;
- a second pair of NPT stacks formed in the solder resist of the package having a second pitch, wherein the first pitch is different than the second pitch;
- a first electrode that extends through a portion of the solder resist and through a first dielectric layer to a second dielectric layer, wherein a first NPT stack of the first pair of NPT stacks contacts the first electrode;
- and
- a second electrode that extends through a portion of the solder resist and through the first dielectric layer to an embedded multi-die interconnect bridge (EMIB) configured to provide high-bandwidth connection between a first die and a second die, wherein a second NPT stack of the second pair of NPT stacks contacts the second electrode.
An apparatus including a package comprising:
- the package comprising:
- a solder resist;
- a first electrode embedded in a bottom portion of the solder resist;
- a solder bump extending through the solder resist to the first electrode, the solder bump including a nickel, palladium, and tin (NPT) stack;
- a second electrode embedded in the bottom portion of the solder resist in parallel with the first electrode;
- a second solder bump extending through the solder resist to the second electrode, the second solder bump including a second NPT stack;
- a third electrode embedded in the bottom portion of the solder resist in parallel with the first electrode and the second electrode;
- a third solder bump extending through the solder resist to the third electrode, the third solder bump including a third NPT stack;
- an embedded multi-die interconnect bridge configured to provide high-bandwidth connection between a first die and a second die electrically coupled to the first NPT stack;
- wherein a pitch between the first solder bump and the second solder bump is different than a pitch between the second solder bump and the third solder bump;
- wherein the first electrode extends through a portion of the solder resist and through a first dielectric layer to a second dielectric layer;
- wherein the first NPT stack contacts the first electrode;
- and
- wherein the second electrode extends through a portion of the solder resist and through the first dielectric layer and contacts the second electrode.
Dependencies are inferred from the claim text.