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US 2018/0323147 A1Published application
3d interconnect multi-die inductors with through-substrate via cores
AssigneeMicron Technology, Inc.
InventorKyle K. Kirby
Life of this patent
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Abstract
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.
Claims10
A semiconductor device, comprising:
- a first die including:
- a first top surface and a first bottom surface,
- a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a top portion extending past the first top surface and a bottom portion extending past the first bottom surface, and
- a first substantially helical conductor disposed around the TSV;
- a second die including:
- a second top surface having an opening in which the bottom portion of the TSV is disposed, and
- a second substantially helical conductor disposed around the opening in the second top surface;
- and
- a third die including:
- a second bottom surface having an opening in which the top portion of the TSV is disposed, and
- a third substantially helical conductor disposed around the opening in the second bottom surface.
8 more elements
10-14. (canceled)
Dependencies are inferred from the claim text.