Back to results
US 2018/0323145 A1Published application
3d interconnect multi-die inductors with through-substrate via cores
AssigneeMicron Technology, Inc.
InventorKyle K. Kirby
Life of this patent
Estimating the term…
Abstract
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.
Claims13
A semiconductor device, comprising:
- a first die including:
- a first surface,
- a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface, and
- a first substantially helical conductor disposed around the TSV;
- and
- a second die including:
- a second surface,
- an opening in the second surface in which the portion of the TSV is disposed, and
- a second substantially helical conductor disposed around the opening.
6 more elements
-26. (canceled)
Dependencies are inferred from the claim text.