Chip package with sidewall metallization

A manufacturing method, comprising:

• forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating;
• bonding a semiconductor wafer on a front side of the carrier wafer so that each of a plurality of electronic chips of the semiconductor wafer is aligned with respect to a respective one of the trenches;
• forming an electrically conductive connection structure at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips;
• and
• removing material on a backside of the carrier wafer to thereby singularize the bonded wafers at the trenches into a plurality of semiconductor devices.