Method And System For Improved Matching For On-Chip Capacitors

A semiconductor device comprising:

• a semiconductor die comprising an on-chip capacitor, said on-chip capacitor comprising:
• a first set of electrically coupled metal fingers;
• and
• a second set of electrically coupled metal fingers that are interdigitated with the first set of electrically coupled metal fingers, wherein:
• the first set of electrically coupled metal fingers and the second set of electrically coupled metal fingers are arranged in sections around a center interconnect;
• and
• the first set of electrically coupled metal fingers is only clockwise-oriented in each section of the on-chip capacitor and the second set of electrically coupled metal fingers is only counter-clockwise-oriented in each section of the on-chip capacitor.

A semiconductor device comprising:

• a semiconductor die comprising an on-chip capacitor, said on-chip capacitor comprising:
• a first layer comprising a first set of electrically coupled metal fingers interdigitated with a second set of electrically coupled metal fingers, wherein the first set of electrically coupled metal fingers and the second set of electrically coupled metal fingers are arranged in sections around a center interconnect;
• and
• a second layer comprising a third set of electrically coupled metal fingers interdigitated with a fourth set of electrically coupled metal fingers, wherein the third set of electrically coupled metal fingers and the fourth set of electrically coupled metal fingers are in the second semiconductor layer, the first and third set of electrically coupled metal fingers are symmetric with respect to the first and second layers, wherein:
• the on-chip capacitor is configured in a sections around a center interconnect;
• and
• the first and third sets of electrically coupled metal fingers are only clockwise-oriented throughout the on-chip capacitor and the second and fourth sets of electrically coupled metal fingers are only counter-clockwise-oriented throughout the on-chip capacitor.

A semiconductor device comprising:

• a complementary metal-oxide semiconductor (CMOS) die comprising an on-chip capacitor and switches that are operable to configure the on-chip capacitor, said on-chip capacitor comprising:
• one or more metal layers;
• and
• first and second sets of electrically coupled interdigitated metal fingers that are arranged around a center interconnect, wherein the first set of electrically coupled fingers is only clockwise-oriented in each section of the on-chip capacitor and the second set of electrically coupled metal fingers is only counter-clockwise-oriented in each section of the on-chip capacitor.