Integration scheme for gate height control and void free rmg fill

A device comprising:

• a dielectric layer over a silicon (Si) fin;
• first and second cavities in the dielectric, each over and perpendicular to the Si fin;
• a high-K dielectric layer on side and bottom surfaces of the first and second cavities;
• a p-type work function (pWF) layer over the high-K dielectric layer in the first and second cavities;
• an n-type work function (nWF) layer over the pWF layer and over edges of the pWF layer in the first cavity and over the high-K dielectric layer in the second cavity;
• and
• a barrier layer over the nWF layer and over edges of the nWF layer,
• wherein the first and second cavities comprise a metal filling with a bump at a center of each cavity.

A method comprising:

• forming an interlayer dielectric (ILD) over a silicon (Si) fin;
• forming first and second cavities in the ILD over and perpendicular to the Si fin, the first cavity having a greater width than the second cavity;
• forming a high-K dielectric layer to a thickness of 5 angstrom (Å) to 25 Å over the ILD and in the first and second cavities;
• forming a p-type work function (pWF) metal layer by atomic layer deposition (ALD) to a thickness of 5 Å to 50 Å in the first and second cavities;
• recessing the pWF metal layer by chamfering to a first height of 2 nanometers (nm) to 25 nm above the Si fin;
• forming an n-type work function (nWF) metal layer by ALD in the cavities over the exposed high-K dielectric layer and the pWF metal layer;
• recessing the nWF metal layer by chamfering to a second height of 4 nm to 30 nm above the Si fin, but covering an edge of the pWF metal layer;
• forming a barrier metal layer by metal organic chemical vapor deposition (MOCVD), ALD, physical vapor deposition (PVD) to a thickness of 25 Å to 75 Å over the high-K dielectric layer and the nWF metal layer;
• filling the first and second cavities with low-resistive metal;
• removing portions of the low resistive metal fill by chemical mechanical planarization (CMP);
• and
• performing reactive ion etching (RIE), recessing the barrier metal layer, the high-K dielectric layer, and the low-resistive metal to a third height 9 nm to 35 nm above the Si fin except for a low-resistive metal to bump or a final gate height extending to 14 nm to 40 nm above the Si fin at a center of each cavity.