US 2018/0323106 A1 · CO-PLANAR P-CHANNEL AND N-CHANNEL GALLIUM NITRIDE-BASED TRANSISTORS ON SILICON AND TECHNIQUES FOR FORMING SAME

Abstract

Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments. Gate stack placement can be customized to provide any desired combination of enhancement and depletion modes for the resultant neighboring p-channel and n-channel transistor devices.

Claims30

Dependent claims

An integrated circuit comprising:

an n-type transistor including
a first layer comprising an oxide and/or a nitride,
second layer over the first layer, the second layer distinct from the first layer and comprising nitrogen and at least one of gallium and indium, and
a third layer over the second layer, the third layer distinct from the second layer and comprising nitrogen and at least one of aluminum, gallium, and indium;
and
a p-type transistor adjacent to the n-type transistor, and including
a fourth layer comprising an oxide and/or a nitride,
a fifth layer over the fourth layer, the fifth layer distinct from the fourth layer and comprising nitrogen and at least one of gallium and indium,
a sixth layer over the fifth layer, wherein at least a portion of the sixth layer is co-planar with at least a portion of the third layer, the sixth layer distinct from the fifth layer and comprising nitrogen and at least one of aluminum, gallium, and indium, and
a seventh layer over the sixth layer, the seventh layer distinct from the sixth layer and comprising nitrogen and at least one of gallium and indium.

7 more elements

An integrated circuit comprising:

a semiconductor substrate;
a dielectric layer over the semiconductor substrate;
first and second features in the semiconductor substrate, under corresponding first and second openings in the dielectric layer, wherein:
the first and second openings are narrower in width than the first and second features, respectively;
and
the first and second features are separated by a portion of the semiconductor substrate;
an n-channel transistor device comprising:
a first buffer layer over the semiconductor substrate, within the first feature;
a first III-N semiconductor layer over the first buffer layer, within the first feature;
and
a first polarization layer over the first III-N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer;
and
a p-channel transistor device comprising:
a second buffer layer over the semiconductor substrate, within the second feature;
a second III-N semiconductor layer over the second buffer layer, within the second feature;
a second polarization layer over the second III-N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer;
and
a third III-N semiconductor layer over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.

15 more elements

An integrated circuit comprising:

a substrate comprising silicon;
a dielectric material over the substrate;
first and second trenches in the substrate, under corresponding first and second openings in the dielectric material, wherein the first and second trenches are separated from one another by a prominence extending from the substrate;
first and second layers on the substrate, within the first and second trenches, respectively, the first and second layers comprising a nitride and/or an oxide;
third and fourth layers on the first and second layers, respectively, within the first and second trenches, respectively, the third and fourth layers comprising nitrogen and at least one of gallium and indium;
fifth and sixth layers distinct from and over the third and fourth layers, respectively, within the first and second trenches, respectively, and extending through the first and second openings, respectively, such that at least a portion of each of the fifth and sixth layers is co-planar with an upper surface of the dielectric material, the fifth and sixth layers comprising nitrogen, aluminum, and at least one of gallium and indium;
and
a seventh layer distinct from and over the at least a portion of the fifth and sixth layers that are co-planar with the upper surface of the dielectric material.

5 more elements

Dependencies are inferred from the claim text.

Co-planar p-channel and n-channel gallium nitride-based transistors on silicon and techniques for forming same

Life of this patent

Co-planar p-channel and n-channel gallium nitride-based transistors on silicon and techniques for forming same

Life of this patent

Abstract

Claims30