Metal via processing schemes with via critical dimension (cd) control for back end of line (beol) interconnects and the resulting structures

A method of fabricating an interconnect structure for a semiconductor die, the method comprising:

• forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate;
• forming an inter-layer dielectric layer above the metallization layer;
• forming a grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer, wherein intersections of the grating pattern and the alternating metal lines and dielectric lines of the lower metallization layer define possible via locations for a metallization layer;
• forming a pattern accumulation layer above the grating pattern;
• patterning the pattern accumulation layer to form a patterned memory layer;
• patterning the inter-layer dielectric layer using the grating pattern and the patterned memory layer to form via locations and line regions in the inter-layer dielectric layer;
• and
• forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

A method of fabricating an interconnect structure for a semiconductor die, the method comprising:

• forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate;
• forming an inter-layer dielectric layer above the metallization layer;
• forming a first grating hardmask layer above the inter-layer dielectric layer, the first grating hardmask layer having a direction orthogonal to the direction of the alternating metal lines and dielectric lines of the lower metallization layer;
• transferring a pattern of the first grating hardmask layer to the inter-layer dielectric layer to form a patterned inter-layer dielectric layer having line regions therein;
• forming a pattern accumulation layer above the first grating hardmask layer;
• forming a second grating hardmask layer above the pattern accumulation layer, the second grating hardmask layer having a direction parallel with the direction of the alternating metal lines and dielectric lines of the lower metallization layer;
• with the second grating hardmask layer in place, transferring a first via pattern to the pattern accumulation layer;
• removing the second grating hardmask layer;
• subsequent to removing the second grating hardmask layer, transferring a second via pattern to the pattern accumulation layer to form a twice patterned memory layer having a pattern;
• transferring the pattern of the twice patterned memory layer to the patterned inter-layer dielectric layer to form a twice patterned inter-layer dielectric layer having via locations therein;
• and
• forming metal vias and metal lines in the via locations and line regions, respectively, of the twice patterned inter-layer dielectric layer.