Method For Increasing Trench CD in EUV Patterning Without Increasing Single Line Opens or Roughness

A method for processing a substrate, comprising:

• providing the substrate with a plurality of first patterned structures, the plurality of first patterned structures having at least a first pitch of 36 nm or less, the first patterned structures having a first line width and first space width;
• providing the substrate with a trim layer underlying the first patterned structures;
• providing the substrate with an intervening layer between the plurality of first patterned structures and the trim layer;
• providing the substrate with a hard mask layer underlying the trim layer;
• etching the intervening layer to provide a plurality of patterned intervening layer structures corresponding to the plurality of first patterned structures;
• etching the trim layer to provide a plurality of patterned trim layer structures corresponding to the plurality of first patterned structures;
• after etching the trim layer, trimming the trim layer with an isotropic etch process to reduce a critical dimension of the plurality of patterned trim layer structures;
• and
• after trimming the trim layer, etching the hard mask layer to provide a plurality of hard mask layer structures having a pitch corresponding to the first pitch but having a second line width that is less than the first line width of the plurality of first patterned structures.

A method for forming a trench in a semiconductor wafer at a back end of line process step, comprising:

• providing a trench pattern in an EUV resist layer on the semiconductor wafer to form a plurality of EUV resist patterned structures, the plurality of EUV resist patterned structures having at least a first pitch of 36 nm or less;
• providing an intervening layer underlying the EUV resist layer, the intervening layer being a planarizing layer;
• providing an oxide layer underlying the intervening layer;
• providing a metal hard mask layer underlying the oxide layer;
• etching the oxide layer to provide a plurality of patterned oxide layer structures corresponding to the plurality of EUV resist patterned structures;
• after etching the oxide layer, performing a chemical oxide removal process on the oxide layer to reduce a line width critical dimension of the plurality of patterned oxide layer structures;
• after performing the chemical oxide removal process, etching the metal hard mask layer to provide a plurality of metal hard mask layer structures having a pitch corresponding to the first pitch but having a metal hard mask line width critical dimension that corresponds to the reduced line width critical dimension of the plurality of patterned oxide layer structures;
• and
• forming the trench in the semiconductor wafer, a trench width being larger than a space of the trench pattern due to performing the chemical oxide removal process.