US 2018/0322932 A1Published application

Prevention of neighboring plane disturb in non-volatile memory

AssigneeSanDisk Technologies LLC

InventorsKirubakaran Periyannan, Daniel Joseph Linnen

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Abstract

Techniques are presented for the prevention and detection of inter-plane disturbs in a memory circuit, where, when concurrently performing memory operations on multiple planes, a defect in one plane can feed back through a common supply node and adversely affect memory operations in another node. To isolate such defects to plane in which the occur, the memory supplies the elements, such as a word line, of different planes from a common supply node through a uni-directional circuit element, such as a diode. In this way, if the voltage on an element in an array gets pulled up to an elevated voltage though a defect, this elevated voltage is stopped from flowing back to the common supply node. Additionally, by comparing the voltage levels on either side of the uni-directional circuit element, it can be determined whether such a defect is present in an array.

Claims21

Dependent claims

An apparatus, comprising:

a first group of memory cells connected to a first word line;
a second group of memory cells connected to a second word line, the second word line different than the first word line;
a voltage supply connected to a node to supply a first voltage level to both of the first word line and the second word line;
a control circuit connected to the first and second groups and to the voltage supply, the control circuit configured to perform one or more memory operations concurrently on the first group and the second group such that both the first word line and the second word line concurrently receive the first voltage level from the node;
and
a first unidirectional circuit element through which the first word line is directly connected to the node when receiving the first voltage level, the first unidirectional circuit element configured to allow current to flow from the node to the first word line and to prevent current from flowing from the first word line to the second word line;
and
a second unidirectional circuit element through which the second word line is directly connected to the node when receiving the first voltage level, the second unidirectional circuit element configured to allow current to flow from the node to the second word line and to prevent current from flowing from the second word line to the first word line.

5 more elements

An apparatus, comprising:

a first group of memory cells;
a second group of memory cells;
a voltage supply connected to a node to supply a first voltage level to both of the first and second groups of memory cells;
a control circuit connected to the first and second groups and to the voltage supply, the control circuit configured to perform one or more memory operations concurrently on the first group and the second group such that both the first group and the second group concurrently receive the first voltage level from the node;
a first unidirectional circuit element connected between the first group and the node, and a second unidirectional circuit element connected between the second group and the node;
a first comparator having a first input connected between the node and the first unidirectional circuit element, a second input connected between the first unidirectional circuit element and the first group of memory cells, and an output based on a voltage level at the second input relative to a voltage level at the first input;
and
a second comparator having a first input connected between the node and the second unidirectional circuit element, a second input connected between the second unidirectional circuit element and the first group of memory cells, and an output based on a voltage level at the second input relative to a voltage level at the first input put,
wherein the control circuit is configured to receive the outputs of the first and second comparators.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/585,680Filed 3 May 2017
Published: 8 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 16/3427
Disturbance prevention or evaluation; Refreshing of disturbed memory data: circuits or methods to prevent or reduce disturbance of the state of a…
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/30
Auxiliary circuits, e.g. for writing into memory: power supply circuits
G11C 16/3459
Arrangements for verifying correct programming or for detecting overprogrammed cells: circuits or methods to verify correct programming of…

Family

US 10,141,064 B1Related patent
US 2018/0322932 A1This patent

From the US filing history. Foreign family members aren’t listed.

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