Apparatus and methods including establishing a negative body potential in a memory cell

A method of operating a memory, comprising:

• applying a first voltage level to a source;
• applying a second voltage level to a selected access line, wherein a difference between the first voltage level and the second voltage level is expected to decrease a threshold voltage level of a memory cell connected to the selected access line;
• electrically floating an unselected access line while applying the first voltage level to the source, wherein the memory cell connected to the selected access line and a memory cell connected to the unselected access line are each selectively connected to the source;
• discharging the source to a third voltage level lower than the first voltage level;
• when a voltage level of the unselected access line reaches a particular voltage level while discharging the source to the third voltage level, applying a fourth voltage level higher than the third voltage level to the unselected access line;
• and
• after discharging the source to the third voltage level, discharging the unselected access line to a fifth voltage level lower than the fourth voltage level.

An apparatus, comprising:

• an array of memory cells;
• and
• a controller to perform access operations on the array of memory cells;
• wherein the controller is configured to:
• establish a negative potential in a body of a memory cell of the array of memory cells;
• and
• initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential.

An apparatus, comprising:

• an array of memory cells;
• and
• a controller to perform access operations on the array of memory cells;
• wherein the controller is configured to:
• advance a timer;
• and
• establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

An apparatus, comprising:

• an array of memory cells arranged in strings of series-connected memory cells;
• and
• a controller to perform access operations on the array of memory cells;
• wherein the controller, during an erase operation on a selected string of series-connected memory cells of the array of memory cells selected for the erase operation, is configured to:
• apply a first voltage level to a source;
• apply a second voltage level to a selected access line connected to a memory cell of the selected string of series-connected memory cells, wherein a difference between the first voltage level and the second voltage level is expected to decrease a threshold voltage level of a memory cell connected to the selected access line;
• electrically float an unselected access line connected to a memory cell of an unselected string of series-connected memory cells while applying the first voltage level to the source, wherein the memory cell connected to the selected access line and the memory cell connected to the unselected access line are each selectively connected to the source;
• discharge the source to a third voltage level lower than the first voltage level;
• when a voltage level of the unselected access line reaches a particular voltage level while discharging the source to the third voltage level, apply a fourth voltage level higher than the third voltage level to the unselected access line;
• and
• after discharging the source to the third voltage level, discharge the unselected access line to a fifth voltage level lower than the fourth voltage level.