Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate

A semiconductor memory device comprising:

• a memory cell unit in which an (N+1) number of memory cells (N is a natural number not less than 1), including charge accumulation layers and control gates formed on the charge accumulation layers, are connected in series;
• an (N+1) number of word lines connected to the control gates of 0-th to N-th memory cells connected in series in a one-to-one correspondence;
• a driver circuit which supplies a voltage to the memory cells;
• and
• an (N+1) number of first transistors which are formed on (N+1) number of element regions provided in a semiconductor substrate, include gate electrodes formed above the element regions with gate insulating films interposed therebetween, and transfer the voltage to the word lines respectively, each of the first transistors including two impurity diffused layers which are formed at the surface of one of the element regions and one of which is connected to the driver circuit and the other of which is connected to one of the word lines,
• wherein the (N+1) number of element regions are electrically separated from one another and the gate electrodes are connected in common, and
• above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.