Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance

A method of performing a read operation of a three-dimensional (3D) flash memory device, the 3D flash memory device comprising a plurality of cell strings, each of the plurality of cell strings including a string select transistor, a plurality of memory cells and a ground select transistor stacked in a direction perpendicular to a substrate, the method comprising:

• applying a first turn-on voltage to a selected string selection line among a plurality of string selection lines connected to a plurality of string selection transistors of the plurality of cell strings;
• applying a second turn-on voltage and a third turn on voltage to a first unselected string selection line and a second unselected string selection line respectively among the plurality of string selection lines;
• applying a fourth turn-on voltage to a selected ground selection line among a plurality of ground selection lines connected to a plurality of ground selection transistors of the plurality of cell strings;
• after applying the first through fourth turn-on voltages the decoder is further configured to adjust a first voltage of the first unselected string selection line to a first level;
• and
• after adjusting the voltage of the first unselected string selection line the decoder is further configured to adjust a second voltage of the second unselected string selection line to a second level,
• wherein string selection transistors, among the plurality of string selection transistors, connected to the selected string selection line and ground selection transistors, among the plurality of ground selection transistors, connected to the selected ground selection line are turned-on while the first voltage and the second voltage are adjusted.

A storage device comprising:

• a controller configured to transmit a read command and an address;
• and
• a three-dimensional (3D) flash memory device comprising a plurality of memory blocks, each of the plurality of memory blocks including a plurality of cell strings, each of the plurality of cell strings including a string select transistor, a plurality of memory cells and a ground select transistor stacked in a direction perpendicular to a substrate;
• and
• a decider configured to, in response to the read command, apply a first turn-on voltage to a selected string selection line among a plurality of string selection lines connected to a plurality of string selection transistors of the plurality of cell strings, apply a second turn-on voltage and a third turn on voltage to a first unselected string selection line and a second unselected string selection line respectively among the plurality of string selection lines in a selected memory block indicated by the address among the plurality of memory blocks,
• wherein the decoder is further configured to, in response to the read command and in the selected memory block, apply a fourth turn-on voltage to a selected ground selection line among a plurality of ground selection lines connected to a plurality of ground selection transistors of the plurality of cell strings,
• after applying the first through fourth turn-on voltages, in response to the read command and in the selected memory block, the decoder is further configured to adjust a first voltage of the first unselected string selection line to a first level,
• after adjusting the voltage of the first unselected string selection line, in response to the read command and in the selected memory block, the decoder is further configured to adjust a second voltage of the second unselected string selection line to a second level, and
• string selection transistors, among the plurality of string selection transistors, connected to the selected string selection line and ground selection transistors, among the plurality of ground selection transistors, connected to the selected ground selection line are turned-on while the first voltage and the second voltage are adjusted in the selected memory block.