Sram margin recovery during burn-in

An apparatus, comprising:

• a latch circuit, wherein the latch circuit contains two NMOS FETs and two PMOS FETs arranged as a first set of CMOS devices and a second set of CMOS devices, wherein each FET includes a gate terminal that is connected to a first surface and a drain terminal that is connected to a second surface, and wherein the first surface and the second surface are of a dielectric material that includes a plurality of atomic vacancies that trap charge carriers and shift a threshold voltage of at least one FET of the two NMOS FETs and the two PMOS FETs in response to applying one or more stresses to the latch circuit;
• and
• two access transistors operatively connected to the latch circuit such that a first access transistor of the two access transistors is connected to the first set of CMOS devices, and a second access transistor of the two access transistors is connected to the second set of CMOS devices.