Gip circuit and driving method therefor, and flat panel display device

A GIP (Gate in Panel) circuit, comprising a plurality of sequentially connected drive units, each drive unit connecting to a drive control line, a first gate line, a second gate line, a first clock signal line and a second clock signal line,

• wherein the drive unit comprises first to eighth transistors, a first capacitor and a second capacitor, the first transistor connected between the drive control line and a first node and having a first gate in connection with the first clock signal line, the second transistor connected between the first clock signal line and a third node and having a second gate in connection with the first node, the third transistor connected between the second clock signal line and a fourth node and having a third gate in connection with the third node, the fourth transistor connected between a second node and the fourth node and having a fourth gate in connection with the second clock signal line, the fifth transistor connected between the third node and the second gate line and having a fifth gate in connection with the first clock signal line, the sixth transistor connected between the first gate line and the second node and having a sixth gate in connection with the first node, the seventh transistor connected between the first gate line and an output terminal and having a seventh gate in connection with the second node, the eighth transistor connected between the second gate line and the output terminal and having an eighth gate in connection with the first node, the first capacitor connected between the third node and the fourth node, the second capacitor connected between the first node and the output terminal.