Field-effect transistor placement optimization for improved leaf cell routability

A computer program product for automatically generating a layout of a cell of a semiconductor circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

• read, by a processor, a netlist of the cell, the netlist including a description of internal electrical nets connecting electrical components of the cell with each other;
• assign, by the processor, an exclusive internal weight to at least one internal net of the internal electrical nets;
• and
• place, by the processor, the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit.

A system, comprising a processor and a memory storing program instructions for automatically generating a layout of a cell of a semiconductor circuit thereon, the program instructions executable by the processor to cause the system to:

• read, by a processor, a netlist of the cell, the netlist including a description of internal electrical nets connecting electrical components of the cell with each other;
• assign, by the processor, an exclusive internal weight to at least one internal net of the internal electrical nets;
• and
• place, by the processor, the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit.