Integrated circuits including cells arranged considering supply voltage variation of cells and influence between cells and design methods thereof

An integrated circuit comprising:

• a first cell of a plurality of cells;
• and
• a second cell of the plurality of cells,
• wherein a location of the first cell within the integrated circuit is arranged according to a plurality of propagation delays of the first cell,
• wherein the plurality of propagation delays comprise:
• a first delay of the first cell generated based on a plurality of power resistances of the first cell and a first switching operation of the first cell;
• and
• a second delay of the first cell generated based on a voltage variation due to a second switching operation of the second cell.

A method of integrated circuit design, comprising:

• extracting a plurality of power resistances of a plurality of paths for supplying power to a plurality of cells of an integrated circuit;
• calculating a plurality of first timing derates indicating a plurality of first delays of the plurality of cells generated by the plurality of power resistances;
• performing a first static timing analysis to calculate a plurality of propagation delays of the plurality of cells by using the plurality of first timing derates and to determine a plurality of arrival timing windows, in which the plurality of cells respectively receive input signals, by using the plurality of propagation delays;
• calculating a plurality of second timing derates indicating a plurality of second delays of the plurality of cells generated as the plurality of arrival timing windows overlap each other;
• performing a second static timing analysis to calculate the plurality of propagation delays by using the plurality of first timing derates and the plurality of second timing derates;
• and
• arranging the plurality of cells or the plurality of paths based on a result of the second static timing analysis.