Scheduling simultaneous optimization of multiple very-large-scale-integration designs

A non-transitory machine-readable storage medium encoded with instructions executable by a processor, the non-transitory machine-readable storage medium comprising:

• instructions to obtain a plurality of synthesis scenarios associated with a very-large-scale integration design, wherein each synthesis scenario of the plurality of synthesis scenarios describes a different combination of tunable design parameters for a macro of the very-large-scale integration design, and wherein the very-large-scale integration design includes a plurality of macros being tuned;
• instructions to rank the plurality of macros, before the plurality of synthesis scenarios is submitted for synthesis by a synthesis tuning system, wherein the ranking produces a macro waiting list, and wherein the macro waiting list identifies those of the plurality of synthesis scenarios that are associated with each of the plurality of macros;
• instructions to push a subset of the plurality of synthesis scenarios from the macro waiting list to a job submission queue, wherein the job submission queue ranks the subset of the plurality of synthesis scenarios in an order in which the subset of the plurality of synthesis scenarios is to be synthesized by the synthesis tuning system;
• instructions to submit a synthesis scenario of the subset of the plurality of synthesis scenarios to the synthesis tuning system according to the order;
• instructions to tune the design parameters of the very-large-scale integration design based on a result of the synthesis tuning run;
• and
• instructions to fabricate an integrated circuit according to the design parameters of the very-large-scale integration as tuned.