Systems and methods for multi-architecture computing

A computing system, comprising:

• a processor system including at least one first processor core having a first instruction set architecture (ISA);
• a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA;
• and
• control logic to resume execution of the program by the at least one first processor core in response to an instruction from a server system, wherein the server system includes at least one second processor core that previously executed the program, and wherein the at least one second processor core has a second ISA different from the first ISA;
• wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA, and wherein the server system is to provide the instruction in response to a determination that a communication link between the server system and the computing system meets one or more impending loss criteria.

A first computing system, comprising:

• a processor system including at least one first processor core having a first instruction set architecture (ISA);
• a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA;
• and
• control logic to stop execution of the program by the at least one first processor core and instruct at a second computing system to resume execution of the program with at least one second processor core of the second computing system, wherein the at least one second processor core has a second ISA different from the first ISA;
• wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.