Computing In Parallel Processing Environments
AssigneeMellanox Technologies, Ltd.
InventorMark Rosenbluth
Life of this patent
Estimating the term…
Abstract
A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.
Claims20
A system comprises:
- a multicore processor device including:
- a plurality of cores, with multiple ones of the plurality of cores each comprising
- a processor;
- and
- switching circuitry configured to couple the processor to a network among the plurality of cores;
- the system further comprising:
- a directory that tracks status of cached lines;
- a cache controller for implementing a cache coherency, with the cache controller configured to:
- receive by the directory a read request from a reader device to read a cache line;
- change in the directory a first state of the requested cache line to a forward state;
- and
- supply the requested read cached line with an owned state to the requesting reader device.
A method of implementing cache coherency in a computing system, the method comprising:
- receiving by a directory in the system, a read request from a reader device to read a cache line;
- changing in the directory a first state of the requested cache line to a forward state;
- and
- supplying the read cached line with an owned state to the requesting reader device.
A computer program product tangible stored in a computer readable, hardware storage device, the product for configuring a cache controller to maintain cache coherency in a system including plural level 2 caches and a multicore processor device, the computer program product comprising instructions to cause a processor to:
- receive by a directory a read request from a reader device to read a cache line from;
- change in the directory a first state of the requested cache line to a forward state;
- and
- supply the requested read cached line with an owned state to the requesting reader device.
Dependencies are inferred from the claim text.