Non-destructive analysis to determine use history of processor

A non-transitory computer readable storage medium comprising a computer readable program for chip testing, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:

• selectively deploying a chip under test for future use or discarding the chip under test to prevent the future use, responsive to a stress history of the chip under test determined using a non-destructive test procedure,
• wherein the non-destructive test procedure comprises:
• ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto;
• ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks;
• and
• calculating a sum by summing the plurality of pattern ranks,
• wherein the sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip under test.

A system for chip testing, comprising:

• an evaluation processor configured to:
• selectively deploy a chip under test for future use or discard the chip under test to prevent the future use, responsive to a stress history of the chip under test,
• wherein the non-destructive test procedure comprises ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the plurality of pattern ranks, and
• wherein the sum calculated during an initial performance of the test procedure is designated as the baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip under test.