Delay circuitry to hold up power to a mass storage device and method therefor

A method for power fail protection of a plurality of non-volatile memory devices in a computer device having an enclosure, a power supply unit, one or more host computers, a midplane and interposer boards to connect non-volatile memory mass storage devices with the one or more host computers, the method comprising:

• configuring a host computer to exchange data and control signals with a selected non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices;
• providing power from a midplane supply voltage source to a multiplexing logic circuit along a data/signal path to the plurality of non-volatile memory mass storage device, and from the midplane supply voltage source to the plurality of non-volatile memory mass storage device;
• and
• automatically triggering a power shutoff, after a predictable time delay, of the plurality of non-volatile memory mass storage devices upon detecting a power fault condition along the data/signal path.

A circuit, comprising:

• a non-volatile memory mass storage device having a volatile memory device and non-volatile data carrier, the volatile memory device configured to cache data prior to storing the data on non-volatile memory data carriers in the plurality of non-volatile memory mass storage devices;
• a power supply providing power, along a first power path, to a logic circuit along a data path to the storage device, and along a second power path to the storage device;
• a power fault detection circuit adapted to remove power from the second power path when a power fault is detected along the first power path;
• and
• a delay circuit configured to delay shutting off the non-volatile memory mass storage device after detection of the power fault along the first power path, the delay circuit providing time for the data to be copied from the volatile memory device to the non-volatile memory data carriers.

A computer device, comprising:

• an enclosure having one or more host computers powered by a power supply;
• a plurality of non-volatile memory mass storage devices;
• a plurality of interposer boards, the one or more host computers communicatively coupled to the plurality of non-volatile memory mass storage devices by the plurality of interposer boards;
• a midplane coupled between the one or more host devices and the plurality of interposer boards;
• where at least one of the host computers in the one or more host devices configured to exchange data and control signals with selected non-volatile memory mass storage devices in the plurality of non-volatile memory mass storage devices;
• and
• where each of the interposer boards in the plurality of interposer boards comprises:
• a first e-fuse to gate power to a logic circuit on the at least one interposer board along a data path to a first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices;
• a second e-fuse to gate power to the first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices, wherein the first and the second e-fuses are logically connected to fault the second e-fuse when a fault condition occurs on the first e-fuse;
• and
• a delay circuit, coupled between the first e-fuse and the second e-fuse, configured to delay the fault of the second e-fuse after the fault of the first e-fuse.